1. Field of the Invention
The present general inventive concept relates to a duty cycle correction circuit apparatus to correct a duty ratio, and more particularly, to an electronic apparatus having a simple duty cycle correction circuit apparatus which can correct a duty ratio to 50:50.
2. Description of the Related Art
Generally, devices operating at high speed, such as analog to digital (A/D) converters and double data rate synchronous dynamic random access memory (DDR SDRAM), are activated by both a rising edge and falling edge of a clock signal. In a case that both a rising edge and a falling edge of a clock signal are used, it is important to maintain a duty ratio of 50:50 in order to improve design margin. In addition, since another duty ratio might be used if necessary, there also is a need to maintain a duty ratio desired by a designer.
Thus, in a dynamic random access memory (DRAM), various interface systems, etc., a conventional duty cycle correction circuit corrects a duty ratio close to 50:50. A conventional duty cycle correction circuit corrects a received single input clock signal in an analog manner, and thus a complicated operation is required. In addition, in a system using multiphase clock signals, duty cycle correction circuits are required as many as multiphase clock signals.